Gray code counter Gray code counters are used in FIFO design because they only allow one bit to change for each clock transition. This characteristic eliminates the problem associated with trying to ...

Abstract: This paper presents the design and implementation of a 128-bit Asynchronous Gray Code FIFO using Verilog HDL. The FIFO is designed for bidirectional transfer of data between different clock ...

The Asynchronous FIFO (First-In-First-Out) is a commonly used design component for safe data transfer between two different clock domains. It uses separate read and write clocks and typically ...