Julien Ryckaert at imec suggests a new approach to heterogeneous integration – instead of heterogeneous packaging, use monolithic heterogeneous on-chip integration. Ryckaert calls the approach ‘CMOS 2 ...

The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new ...

As transistors are scaled to smaller dimensions, their static power increases. Combining two-dimensional (2D) channel materials with complementary metal–oxide–semiconductor (CMOS) logic architectures ...

Nottingham-based SFN (Search for the Next) has characterised its novel transistor-based logic, and claims that it matches CMOS performance even when made in older fabs. It would “enable chip designers ...

Continuing the rapid expansion of its standard logic product line, Diodes Incorporated has announced the availability of more package options added to its four families of high-speed and advanced high ...

Before we plunge headfirst into the fray with gusto and abandon (and aplomb, of course), let’s remind and reassure ourselves that—although the following discussions focus on the devices and ...