EDN

How To Interface DDR-II SRAMs with Stratix II Devices

Synchronous static RAM (SRAM) architectures are evolving to support the high-throughput requirements of communications, networking, and digital signal processing (DSP) systems. Previous Sync SRAM ...
EDN

Overcoming DDR-2-interface challenges

DDR (double-data-rate) memory devices do an admirable job of unclogging the memory bottleneck between external memory and ASICs, but the nature of DDR is stretching the skills of designers creating ...
Design-Reuse

Synopsys' DesignWare DDR PHY Compiler Eases Integration of Memory Interface IP

MOUNTAIN VIEW, Calif., Jan. 26, 2011-- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the immediate ...
Design-Reuse

DFI Technical Group Releases Latest High-Speed Memory Controller and PHY Interface Specification

SAN JOSE, CA, Sep 19, 2011 -- The DDR PHY Interface (DFI) Technical Group today released the preliminary DFI 3.0 specification, the latest version of the pervasive industry specification that defines ...
GitHub

ddr_topology_def.h

enum mv_ddr_rtt_nom_park_evalue rtt_park[MAX_CS_NUM]; enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM]; enum mv_ddr_dic_evalue dic; /* phy electrical configuration */ struct mv_ddr_phy_edata { enum mv_ddr ...
GitHub

mv_ddr_topology.h

#define MV_DDR_64BIT_ECC_PUP8_BUS_MASK 0x1ff #define MV_DDR_32BIT_ECC_PUP8_BUS_MASK 0x10f #define MV_DDR_CS_BITMASK_1CS 0x1 #define MV_DDR_CS_BITMASK_2CS 0x3 #define MV_DDR_ONE_SPHY_PER_DUNIT 1 ...