IEEE

A multiplexer based decoder for flash analog-to-digital converters

Abstract: A decoder for flash analog-to-digital converters with short critical path, regular structure, and small area is presented. The decoder is based on 2:1 multiplexers connected as a tree. Each ...
EDN

3-to-8 Line Decoder/Multiplexer

The 74AHC138 and 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138 and ...
IEEE

Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits

Abstract: Quaternary logic is very suitable for encoded realization of binary logic functions by grouping 2-bits together into quaternary digits. This sort of quaternary encoded reversible realization ...