GitHub

SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation

This repository contains the resources, code, and documentation supporting our work on training a model for HLS-C++ code generation. Our work demonstrates how to leverage transformer-based ...
Semiconductor Engineering

Challenges In Using HLS For FPGA Design

High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved ...
GitHub

heston_kernel_sl_hls.cpp

#pragma HLS interface ap_none port=log_spot_price #pragma HLS resource core=AXI4LiteS metadata="-bus_bundle params" variable=log_spot_price #pragma HLS interface ap_none port=reversion_rate_TIMES_step ...
Semiconductor Engineering

Optimize MATLAB C/C++ Code For HLS

A common use case for high-level synthesis (HLS) is taking 3rd party generated or legacy C/C++ algorithms and converting the algorithm to a hardware implementation using an HLS compiler. This can ...
IEEE

LLM vs HLS for RTL Code Generation: Friend or Foe?

Abstract: High-Level Synthesis (HLS) tools are widely used for the efficient transformations of behavioural code into equivalent hardware in Register Transfer Level (RTL). However, recent studies show ...