Abstract: In this paper, we propose three modular multiplication algorithms that use only the IEEE 754 binary floating-point operations. Several previous studies have used floating-point operations to ...
A SystemVerilog implementation of an IEEE 754 double-precision floating point subtractor, verified at RTL level and pushed through full ASIC physical design using the OpenLane flow on the sky130 PDK.
Abstract: Published in "IEEE Transactions on Emerging Topics in Computing, Volume: 9, Issue: 3, JulySeptember 2021" and orally presented at ARITH 2021. Published in: 2021 IEEE 28th Symposium on ...
In 1985, the Institute of Electrical and Electronics Engineers (IEEE) established IEEE 754, a standard for floating point formats and arithmetic that would become the model for practically all FP ...
The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The pipelined design combines high throu ...
All custom made Verilog modules could complete execution in 1 clock cycle using an Intel Altera Cyclone V 5CSEMA5F31C6N FPGA clocked @ 50 MHz. Note that the CORDIC module was discovered to only be ...
Beforediscussing a new approach that enables floating-point implementation inhardware with performance similar to that of fixed-point processing, it isfirst necessary to discuss the reason why ...
[Editor's note: For an intro to fixed-point math, see Fixed-Point DSP and Algorithm Implementation. For a comparison of fixed- and floating-point hardware, see Fixed vs. floating point: a surprisingly ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results