This repository contains two implementations of a phase-locked loop (PLL) on a FPGA (field-programmable gate array). We use the Labview graphical programming environment to generate FPGA binary code ...
Abstract: This paper proposes a novel three-phase phase-locked loop (PLL) algorithm, which focuses on the reforming of the primary signals before grid synchronization rather than improving the phase ...
Abstract: This paper proposed a synchronous PWM method of parallel AC-DC converters. The parallel AC-DC converters of traction control system for high speed train require accurate PLL (Phase-Locked ...
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