The vlsi folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 ...

The vlsi folder of this repository contains an example Hammer flow with the TinyRocketConfig from Chipyard. This example tutorial uses the built-in Sky130 technology plugin and OpenROAD tool plugin.

RISC-V International manages the RISC-V open source instruction set. It is supported by a range of tools and compilers. This TechXchange includes content that takes a look at those tools. In this ...

The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), ...

With its blend of open-source freedoms with the benefits of standardization, the RISC-V (risk-five) Foundation is attracting widespread industry interest. Its core specifications are stable and on the ...

This webinar by SiFive, a developer of RISC-V cores, introduces the RISC-V Architecture. It will provide an overview of RISC-V Modes, Instructions and Extensions, Control and Status Registers, and ...

Munich, Germany – April 13 th, 2021 – Codasip, the leading supplier of processor design solutions and customizable RISC-V processor IP, is pleased to announce the availability of Codasip Studio 9.0 ...

The push for open source isn’t limited just to software; in fact, there’s quite a big push for open-source hardware as well. Founded in 2015, the RISC-V (pronounced “risk five”) Foundation, now RISC-V ...

RISC architecture might change the world, but it runs an NES emulator right now. That’s thanks to MaixPy, the new MicroPython for the K210, the recently released RISC-V microcontroller that’s making ...

If you wanted to make a CPU, and you’re not AMD or Intel, there are two real choices: ARM and RISC-V. But what are the differences between the two, and why do companies choose one over the other?