The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), ...
A new RISC-V Tensor Unit, based on fully customizable 64-bit cores, claims to provide a huge performance boost for artificial intelligence (AI) applications compared to just running software on scalar ...
A new technical paper titled “Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions” was published by researchers at the Tampere University. “Custom instruction (CI) ...
The DeepComputing DC-ROMA RISC-V Mainboard is built around the open-source RISC-V instruction set architecture (ISA), providing a platform for experimentation and customization. Its modular design and ...
If you enjoy portable devices and anything equipped with the RISC-V architecture you’re sure to in joy this introduction to the first RISC-V Cyberdeck, marking a significant milestone in the world of ...
Experts At The Table: Despite growing excitement and participation in the development of the RISC-V ecosystem, significant holes remain in the development flow. One of the most concerning is ...
Forbes contributors publish independent expert analyses and insights. Dave Altavilla is a Tech Analyst covering chips, compute and AI. For decades, chip architectures have been dominated by a pair of ...
The crux of most supercomputers is the ability to operate on many pieces of data at once — something video cards are good at, too. Enter T1 (short for Torrent-1), a RISC-V vector inspired by the Cray ...
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