EDN

PCI Express x1 PHY supports source synchronous and DDR clocking

Dallas, Tex.— Texas Instruments Inc.'s PCI Express (PCIe) x1 physical layer (PHY) chip has hit the market in volume, providing a low-cost PCI Express endpoint device for a wide variety of sectors such ...
Design-Reuse

Altera FPGA Enables Industry's Highest Source-Synchronous Data Transfer Rate

Stratix GX Device with Embedded DPA Circuitry Is Industry's Only FPGA Supporting 1-Gbps SPI-4.2 Signaling San Jose, Calif., May 20, 2003— Altera Corporation (NASDAQ: ALTR) today announced that its ...
Semiconductor Engineering

Clocks Getting Skewed Up

At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it’s fraught with the most problems at the ...
New Electronics

Clocking is critical

Frequency management will play an important role if Ethernet is to be applied successfully in synchronous networks. The convergence of datacom and telecom networks is placing new challenges on network ...