GitHub

sync_fifo_design.v

localparam fifo_depth_log = $clog2(fifo_depth); // taking fifo depth in decimal value using log function to represent no. of bits required to represent 8 // declare a ...
GitHub

manar774/Synchronous-_FIFO-_VERIFICATION

/FIFO_top/DUT/SVA_wr_ack_coverage 3500 Covered /FIFO_top/DUT/SVA_overflow_coverage 245 Covered /FIFO_top/DUT/SVA_underflow_coverage 241 Covered /FIFO_top/DUT/SVA ...
LinkedIn

Verilog HDL Synchronous FIFO Design and Verification Project

Completed a Synchronous FIFO Design and Verification project using Verilog HDL. Project Highlights: • Designed parameterized synchronous FIFO architecture • Implemented read/write pointer logic with ...
LinkedIn

Kunal Jha’s Post

🚀 Synchronous FIFO Design – Full & Empty Condition Verification 🚀 Recently, I worked on the design and verification of a Synchronous FIFO using Verilog/SystemVerilog, focusing on wrap-around ...
IEEE

A Low-Power Synchronous FIFO Using Gray Code Pointers and Word-Level Clock Gating

Abstract: In present low-power digital systems, first-in, first-out (FIFO) memories are essential parts for data rate matching and buffering. Due to frequent switching in memory components and clock ...
Design-Reuse

Design Transition from Sync to Async: Design and Verification Challenges

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...