Semiconductor Engineering

Seeing Is Believing: Visualizing Full Coverage Closure In Low-Power Designs

Lowering the power consumption and leakage in SoCs and other electrical designs has become a paramount concern in recent years. The reasons for this are many and well understood. The structures and ...
Semiconductor Engineering

Simplifying SystemVerilog Functional Coverage

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is ...
Design-Reuse

Imperas leads the RISC-V verification ecosystem as the first to release an open-source ...

Complete source file access allows easy adoption and enables user extensions for advanced microarchitecture verification that helps all RISC-V projects accelerate time-to-market goals Design ...
New Electronics

Open-source SystemVerilog RISC-V processor functional coverage library

Imperas Software has announced the release of the first open-source SystemVerilog RISC-V processor functional coverage library for RISC-V cores. The initial release is for RV32IMC, RV64 and other ...