Electronics Weekly

Imec develops die-to-wafer bond process with 2µm pad pitch

Imec has developed a Cu-to-Cu and SiCN-to-SiCN die-to-wafer bonding process resulting in a Cu bond pad pitch of only 2µm at <350nm die-to-wafer overlay error, achieving good electrical yield. Such ...
Semiconductor Engineering

New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to-Wafer Bonding Technology

How a real chip-last process flow with a chip-to-wafer (C2W) bonding technology can address the RDL-base Interposer PoP challenge. Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has ...
Semiconductor Engineering

Solving Fan-Out Wafer-Level Warpage Challenges Using Material Science

Now more than ever we’re finding that semiconductor process engineers are turning to material scientists to help find solutions for their most complex challenges. Currently, they are looking for ways ...