Design-Reuse

Altera Delivers Major Advancements for High-Density Designs With Quartus II Software ...

First FPGA Vendor to Provide Comprehensive Native Support for the Synopsys Design Constraints (SDC) Format in its Design Software San Jose, Calif., May 8, 2006—Altera Corporation (NASDAQ: ALTR) ...
マイナビニュース

Altera、開発ソフトウェア「Quartus II」の28nm対応版となるv10.0を発表

Alteraは、同社のFPGA開発ソフトウェア「Quartus II」の最新バージョン「Quartus II v10.0」を発表した。 同バージョンは、同社の新製品である28nmプロセス採用FPGA「Stratix V」ファミリとして「Stratix V GX」および「Stratix V GS」がサポートされた。 また、配置配線 ...
EDN

Altera suite handles complexity

SANTA CRUZ, Calif. — As design complexity increases, FPGA tools and design flows are looking more and more like ASIC design. Altera Corp. is accelerating that trend this week, with its Quartus 6.0 ...
EDN

FPGA TOOLS: Altera suite handles complexity

Santa Cruz, Calif. — As design complexity increases, FPGA tools and design flows are looking more and more like ASIC design. Altera Corp. is accelerating that trend this week, with its Quartus 6.0 ...
Electronic Design

FPGA Design Suite Builds In Timing Analysis With Native Support For SDC Format

With FPGAs pushing aside ASICs in many complex designs, the limits of traditional FPGA timing-analysis tools are being stressed to the breaking point. So if you want to use today's high-end FPGAs in ...
CIOL

Altera unveils Quartus II v8.1

BANGALORE, INDIA: Reaffirming its leadership position in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs, Altera Corp. today unveiled Quartus II software version 8.1. This ...
Design-Reuse

Altera Continues Its Productivity Leadership Position With Quartus II Software Version 8.1

San Jose, Calif., November 3, 2008—Reaffirming its leadership position in performance and productivity for CPLD, FPGA, and HardCopy ® ASIC designs, Altera Corporation (NASDAQ: ALTR) today unveiled ...