GitHub

Competition MIPS32 Xilinx 32-core Processor Block

This repository contains the Verilog code for my 32-core MIPS32 processor on FPGA. I wrote it for the processor on FPGA designed competition in the Computer Architecture course ECE 369 at the ...
GitHub

ECE 369 MIPS32 SAD assembly code

This repository contains the MIPS32 assembly code for my Sum of Absolute (SAD) Differences algorithm. I wrote it for the Computer Architecture course ECE 369 at the University of Arizona. It can run ...
IEEE

A low power architecture of real time stereo vision algorithm using discrete cosine transform

Abstract: This paper presents a low power architecture of a stereo vision algorithm, that runs in real-time. This algorithm is a modification to the conventional Sum of Absolute Difference (SAD) ...
IEEE

Sum of Absolute Differences algorithm in stereo correspondence problem for stereo matching in computer vision application

Abstract: This paper presents a method to solve the correspondence problem in matching the stereo image using Sum of Absolute Differences (SAD) algorithm. The computer vision application in this paper ...